Abstract:This work addresses the problem of low power design in high-level synthesis in the scenario of the resources operating at multiple voltages. The problem of resource-and-latency constrained scheduling is tackled and a novel methodology for scheduling as well as design space exploration is proposed. The proposed methodology achieves maximal power reduction of functional units by identifying the maximal parallelism of power hungry operators in resource-constrained/time-constrained designs. A novel scheme is devised for recognizing the ‘‘zones’’ of parallel operators that result in maximal power savings when rescheduled to lower voltages. The proposed methodology is developed in the framework of a modified stochastic evolution mechanism in order to tame the computational complexity.
The proposed scheduling technique is extremely fast and it runs in O (n2) where n is the number of the nodes in the data flow graph of the design. This is the fastest reported time of scheduling algorithms for resource and latency constrained scheduling with resources operating at multiple voltages. The algorithm produces results within accuracy of 3–5% of the integer-linear-programming based (i.e., exponential-time complexity) method. The details and the analysis of the results on the standard high-level synthesis benchmarks are provided. Further, analysis of schedules is given for considering generation of control signals for switching the resources. This is the first work to consider such analysis besides proposing an efficient algorithm.
