Funded Project
Start Date : 01 Jan 1900-01 Jan 1900
Reconfigurable Computing and Field-Programmable Gate Arrays (FPGAs) have been used in recent years to implement many complex algorithms into hardware to obtain outstanding performance compared to software solutions. The FPGA solutions have also been used in industrial applications to substitute Application Specific Integrated Circuits wherever flexibility is needed. Dynamic Partial Reconfiguration (DPR) is one of the major developments in the reconfigurable computing area. It is the ability to reprogram a portion of the FPGA without powering down resetting the chip. Hence, DPR offers a new design space with lower configuration time, lower memory consumption and lower power consumption in comparison with the standard reconfigurable computing. In this project, students will explore the theory behind the DPR and all related technical aspects. They will choose an application from security networking field and analyze the algorithm of the chosen application in order to apply the DPR on it. Finally, they will implement their work on the FPGA boards provided by the FPGA lab at the AASTMT and compare their results with other published results.