Funded Project
Start Date : 02 Jun 2013-02 Jun 2013
The Globally Asynchronous Locally Synchronous- based (GALS) Security Processor is based on the Transport Triggered Architecture (TTA) - a dataflow-oriented architecture - which offers higher throughput due to the fact that it parallels the nature of cryptographic algorithms. Internally, the processor is partitioned into 6 regions (1 instruction region, 4 execution regions, and 1 region for interconnection among regions). Each execution region contains a number of Function Units (FU) typically encountered in the implementation of encryption algorithms. FUs grouped in the same execution region are ed to have comparable delay performance. Moreover, each region is governed by its own clock frequency, which allows each FU to run at its own frequency and this – again – contributes to higher throughput. In addition, the decoupled structure of the GALS units makes it possible to clock gate idle regions and thereby reducing the amount of dissipated power. Finally, the asynchrony of regions, in addition to a novel data scrambling technique, renders the processor higher immunity against side channel attacks.